1. Field of the Invention
The present invention relates to a package structure and a manufacturing method thereof. In more detail, the present invention relates to a package structure and a manufacturing method thereof in which a coreless substrate with circuits has direct electrical connections to a semiconductor chip.
2. Description of Related Art
As the electronics industry develops rapidly, research moves towards electronic devices with multiple functions and high performance. Hence, circuit boards with many active and passive components and circuit connections integrated therein have advanced from being single-layered boards to multi-layered boards by an interlayer connection technique, so as to expand circuit layout space in a limited circuit board to thereby meet the demand of the application of high-density integrated circuits.
With regard to conventional semiconductor package structures, a chip is mounted on the top surface of a packaging substrate, and then electrically connected thereto by wire bonding. Alternatively, the chip is electrically connected with the top surface of the substrate by the flip chip technique. Then, electrical connections to a printed circuit board can be achieved by disposing solder balls on the back surface of the substrate. However, even though the purpose of high quantity pin counts can be achieved through the method illustrated above, the electrical performance of a device operated in higher frequency or at higher speed can be unavailable or limited due to the long paths of conductive circuits.
An advanced structure of a flip chip ball grid array (FCBGA) packaging substrate is shown in FIG. 1. In the manufacturing of the FCBGA package structure, a semiconductor chip 10, which has electrode pads 101 on an active surface used for signal input and output, is first provided. Solder bumps 11 are formed on the electrode pads 101 and electrically connect to the bump pads 121a disposed on a substrate 12 having a core layer 120. The substrate 12 here has a plurality of wiring layers 122 and insulation layers 123. In addition, two of wiring layers 122 are electrically connected to each other by conductive vias 125. Moreover, a solder mask 13a is formed on a top wiring layer 122a of the substrate 12 to protect the top wiring layer 122a and to expose the bump pads 121a. Furthermore, the core layer 120 has a plurality of plated through holes 124 conducting the wiring layers 122 on both the surfaces thereof. A bottom wiring layer 122b of the substrate 12 has a plurality of ball pads 121b. Besides, a solder mask 13b is formed on the bottom wiring layer 122b so as to protect the bottom wiring layer 122b and to expose the ball pads 121b. Solder balls 14 are formed on the ball pads 121b to offer electrical connections for a printed circuit board (not shown). Finally, a flip chip ball grid array packaging substrate is obtained.
Even though a flip chip ball grid array packaging substrate could meet the requirement of high quantity pin counts and be used in a device operated in high frequency, there are many limitations in this technique, especially regarding electrical connections. That is, the material used in electrical connections (e.g. solder materials containing Pb) may be prohibited for application due to environmental protection. Furthermore, other alternative materials still have electrical and mechanical problems, such as unstable quality of connections, and those problems are still awaiting solutions. Besides, a conventional flip-chip package structure is electrically connected to a semiconductor chip by solder bumps. During the process of manufacturing fine circuits, filling of a gap between the semiconductor chip and the packaging substrate with resin is required. However, resin is viscous and does not easily flow into the gap, thus the finer the circuits of a packaging substrate, the longer the time needed for filling with the resin. Additionally, there are many unfilled voids in the resin filled region, resulting in increased risk of bust-up of the package structure.
Otherwise, the aforementioned substrate 12 having the core layer 120 is formed by way of the following steps. First, circuit formation is performed on a dielectric layer, and then the core layer 120 is obtained. Manufacturing of a built-up structure is subsequently performed on the core layer 120 so that the substrate 12 has a plurality of circuit layers. Additionally, the core layer 120 has a plurality of plated through holes 124 (PTHs) formed therein. In general, the diameter of the plated through holes 124 is about 100 μm or more. The diameter of the conductive vias is about 50 μm. However, the formed plated through holes 124 compromise the flexibility of the fine circuit layout. Hence, reduction of conductive paths in the substrate 12 is limited, and the electrical characteristics could not be well improved. Furthermore, the thickness of the substrate 12 could not be decreased efficiently because of the existence of the core layer 120. On the other hand, if the core layer 120 is thinned to 60 μm or less, it is difficult to produce the substrate 12, and further results in great reduction in the yield of the substrate 12. Therefore, the core layer 120 does not favor reduction of the whole thickness of the package structure, thus the demands of compact and lightweight electronic devices have not been met.
In the manufacturing of the foregoing substrate with multiple circuit layers, the core layer needs to be prepared first. Subsequently, the dielectric layers and circuit layers stacked on the core layer are formed to obtain a multilayered substrate. These steps of the manufacturing are complex and not easily simplified.
Therefore, the issue of how to provide a circuit board structure, or a method for manufacturing the same to avoid limitations as the mentioned above, e.g. reduction of the substrate thickness, an increase of circuit layer density, good yield of products, and simplification of the manufacturing, is important in this field.